1. Field of the Invention
The present invention relates to semiconductor devices, and particularly relates to a semiconductor device which adjusts a data-signal output timing based on a clock signal.
2. Description of the Related Art
Synchronous semiconductor devices such as an SDRAM (synchronous dynamic random access memory) operate in synchronism with a reference clock signal that is supplied thereto from an exterior of the device, or operate while keeping a predetermined phase relation with the reference clock signal. To achieve such synchronization, semiconductor devices have a control-clock-signal generation circuit provided therein for the purpose of adjusting internal operation timings.
One example of such a control-clock-signal generation circuit is a DLL (delay locked loop) circuit, which adjusts a propagation delay of a reference clock signal inside the device. The DLL circuit typically includes a variable-delay unit for delaying a reference clock signal to output a control clock signal having a predetermined timing, and includes a delay-adjustment unit for adjusting the delay of the reference clock signal based on the phase comparison between the reference clock signal and the delayed reference clock signal.
The control clock signal that is output from the DLL circuit is supplied to an output circuit via a clock buffer where the output circuit outputs a data signal, so that the control clock signal controls the operation timing of the output circuit. Such a DLL circuit has a configuration such as that disclosed in Japanese Patent Laid-open Application No. 10-112182.
In general, a DLL circuit uses a dedicated power voltage in order to prevent its operation from being affected by power noise. A clock buffer provided between the DLL circuit and an output circuit, however, utilizes an internally reduced power voltage that is also used by other circuits provided nearby.
Unfortunately, the internally reduced power voltage may suffer voltage fluctuation. When this happens, a control clock signal, which is supplied from the DLL circuit to the output circuit via the clock buffer, may have jitters because the clock buffer uses the internally reduced power voltage. Jitters end up being fed back to the DLL circuit, thereby reducing phase adjustment accuracy of the DLL circuit.
To avoid this, the clock buffer may be designed to use the same dedicated power voltage that is used by the DLL circuit. A layout restriction of the semiconductor device makes this option difficult. Further, such a design ends up creating noise in the dedicated power voltage provided for the DLL circuit. Noise in the power voltage for dedicated use by the DLL circuit results in a lower accuracy of phase adjustment in the DLL circuit.
Decreases in adjustment accuracy of the DLL circuit are generally main factors that degrade performance of the semiconductor devices.
Accordingly, there is a need for a semiconductor device which can reduce influence of power noises do as to adjust a signal-output timing based on an accurate control clock signal.